CXSD62104双降压恒时同步的PWM控制器两个低损耗稳压器PWM1和PWM2的输出可以从2V调整到5.5V

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发表时间：2020-04-22浏览次数：134

CXSD62104双降压恒时同步的PWM控制器两个低损耗稳压器PWM1和PWM2的输出可以从2V调整到5.5V

目录ZSq嘉泰姆

1.产品概述         2.产品特点ZSq嘉泰姆
3.应用范围       4.下载产品资料PDF文档 ZSq嘉泰姆
5.产品封装图                     6.电路原理图             ZSq嘉泰姆
7.功能概述       8.相关产品ZSq嘉泰姆

一,产品概述(General Description) ZSq嘉泰姆

The CXSD62104 integrates dual step-down, constant-ontime, synchronousZSq嘉泰姆

PWM controllers (that drives dual N-channel MOSFETs for each channel) andZSq嘉泰姆
two low drop-out regulators as well as various protections into a chip.The PWMZSq嘉泰姆
controllers step down high voltage of a battery to generate low-voltage for NBZSq嘉泰姆
applications. The output of PWM1 and PWM2 can be adjusted from 2V to 5.5VZSq嘉泰姆
by setting a resistive voltage-divider from VOUTx to GND.The linear regulatorsZSq嘉泰姆
provide 5V and 3.3V output for standby power supply. The linear regulatorsZSq嘉泰姆

provide up to 100mA output current. When the PWMx output voltage is higher ZSq嘉泰姆

than LDOx bypass threshold, the related LDOx regulator is shut off and its ZSq嘉泰姆

output is connected to VOUTx by internal switchover MOSFET. It can save power dissipation.ZSq嘉泰姆
The CXSD62104 provides excellent transient response and accurate DC ZSq嘉泰姆

output voltage in either PFM or PWM Mode.In Pulse-Frequency Mode (PFM), ZSq嘉泰姆

the CXSD62104 provides very high efficiency over light to heavy loads with ZSq嘉泰姆

loading-modulated switching frequencies. The Forced-PWM mode works nearly ZSq嘉泰姆

at constant frequency for low-noise requirements. The unique ultrasonic modeZSq嘉泰姆

maintains the switching frequency above 25KHz, which eliminates noise in audio applications.ZSq嘉泰姆

The CXSD62104 is equipped with accurate sourcing cur-rent-limit, outputZSq嘉泰姆

under-voltage and output over-voltage protections, being perfect for NB ZSq嘉泰姆

applications. A 1.7ms (typ.) digital soft-start can reduce the start-up current. ZSq嘉泰姆

A soft-stop function actively discharges the output capaci-tors by the discharge ZSq嘉泰姆

device. The CXSD62104 has individual enable controls for PWM channels and ZSq嘉泰姆

LDOs. Pulling both ENPWM pin and ENLDO pin low shuts down the whole chipZSq嘉泰姆

with low quiescent current close to zero.ZSq嘉泰姆
The CXSD62104 is available in a TQFN4x4-24A package.ZSq嘉泰姆
二.产品特点(Features)ZSq嘉泰姆
Wide Input Voltage Range from 6V to 25VZSq嘉泰姆
Provide 4 Independent Outputs with ±1.5% Accu-ZSq嘉泰姆
racy Over-TemperatureZSq嘉泰姆
- PWM1 Controller with Adjustable (2V to 5.5V) Out-putZSq嘉泰姆
PWM2 Controller with Adjustable (2V to 5.5V) Out-putZSq嘉泰姆
100mA Low Dropout Regulator (LDO5) with Fixed 5V OutputZSq嘉泰姆
100mA Low Dropout Regulator (LDO3) with Fixed 3.3V OutputZSq嘉泰姆
Excellent Line/Load Regulations about ±1.5% Over-Temperature RangeZSq嘉泰姆
±1%, (±1.5%, 50μA) 2.0V Reference Voltage OutputZSq嘉泰姆
Built-In POR Control Scheme ImplementedZSq嘉泰姆
Selectable Forced-PWM or Automatic PFM/PWMZSq嘉泰姆
(with Selectable Ultrasonic Operation)ZSq嘉泰姆
Constant-On-Time Control Scheme with FrequencyZSq嘉泰姆
Compensation for PWM ModeZSq嘉泰姆
Selectable Switching Frequency in PWM ModeZSq嘉泰姆
Built-in Digital Soft-Start for PWM Outputs and Soft-ZSq嘉泰姆
Stop for PWM Outputs and LDO OutputsZSq嘉泰姆
Integrated Bootstrap Forward P-CH MOSFETZSq嘉泰姆
High Efficiency over Light to Full Load Range (PWMs)ZSq嘉泰姆
Built-in Power Good Indicators (PWMs)ZSq嘉泰姆
Independent Enable Inputs (PWMs, LDO)ZSq嘉泰姆

70% Under-Voltage and 125% Over-Voltage Protec-tions (PWM)ZSq嘉泰姆

Adjustable Current-Limit Protection (PWMs)ZSq嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)ZSq嘉泰姆
Over-Temperature ProtectionZSq嘉泰姆
4mmx4mm Thin QFN-24 (TQFN4x4-24A) packageZSq嘉泰姆
Lead Free and Green Device Available (RoHS Compliant)ZSq嘉泰姆

三,应用范围 (Applications)ZSq嘉泰姆

Notebook and Sub-Notebook ComputersZSq嘉泰姆

Portable DevicesZSq嘉泰姆
DDR1, DDR2, and DDR3 Power SuppliesZSq嘉泰姆
3-Cell and 4-Cell Li+ Battery-Powered DevicesZSq嘉泰姆
Graphic CardsZSq嘉泰姆
Game ConsolesZSq嘉泰姆
TelecommunicationsZSq嘉泰姆

四.下载产品资料PDF文档 ZSq嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！ZSq嘉泰姆

QQ截图20160419174301.jpg ZSq嘉泰姆

五,产品封装图 (Package)ZSq嘉泰姆

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六.电路原理图ZSq嘉泰姆

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七,功能概述ZSq嘉泰姆

Input Capacitor SelectionZSq嘉泰姆
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, selectZSq嘉泰姆
the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMSZSq嘉泰姆
current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci-tors have to handle large amount of surge current. In low-duty notebook appliactions, ceramic capacitors areZSq嘉泰姆
remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-ZSq嘉泰姆
side MOSFET with very low-impeadance PCB layout. ZSq嘉泰姆
MOSFET SelectionZSq嘉泰姆
The application for a notebook battery with a maximum volt-age of 24V, at least a minimum 30V MOSFETs shouldZSq嘉泰姆
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:ZSq嘉泰姆
· For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFETZSq嘉泰姆
driver will not charge the miller capacitor of this MOSFET.ZSq嘉泰姆
In the turning off process of the low-side MOSFET,the load current will shift to the body diode first. TheZSq嘉泰姆
high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driverZSq嘉泰姆
sinking current path. This results in much less switching loss of the low-side MOSFETs. The dutyZSq嘉泰姆
cycle is often very small in high battery voltage applications, and the low-side MOSFET will con-ZSq嘉泰姆
duct most of the switching cycle; therefore, the less the RDS(ON) of the low-side MOSFET, the less the powerZSq嘉泰姆
loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFETZSq嘉泰姆
does not have this zero voltage switching condition, and because it conducts for less timeZSq嘉泰姆
compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be givenZSq嘉泰姆
to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.ZSq嘉泰姆
The selection of the N-channel power MOSFETs are de-termined by the RDS(ON), reversing transfer capacitanceZSq嘉泰姆
(CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduc-ZSq嘉泰姆
tion loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given byZSq嘉泰姆
the following equations:ZSq嘉泰姆
Layout ConsiderationZSq嘉泰姆
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.ZSq嘉泰姆
With power devices switching at higher frequency, the resulting current transient will cause voltage spike acrossZSq嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionZSq嘉泰姆
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,ZSq嘉泰姆
current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. Any parasiticZSq嘉泰姆
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short andZSq嘉泰姆
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike. AndZSq嘉泰姆
signal and power grounds are to be kept separating and finally combined to use the ground plane construction orZSq嘉泰姆

single point grounding. The best tie-point between the signal ground and the power ground is at the negativeZSq嘉泰姆
side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are notZSq嘉泰姆
recommended. Below is a checklist for your layout:ZSq嘉泰姆
Layout Consideration (Cont.)ZSq嘉泰姆
Keep the switching nodes (UGATEx, LGATEx, BOOTx,and PHASEx) away from sensitive small signal nodesZSq嘉泰姆
(REF, ILIMx, and FBx) since these nodes are fast mov-ing signals. Therefore, keep traces to these nodes asZSq嘉泰姆
short as possible and there should be no other weak signal traces in parallel with theses traces on any layer.ZSq嘉泰姆

Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce ofZSq嘉泰姆

CXSD62104ZSq嘉泰姆

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Part_No ZSq嘉泰姆	Package ZSq嘉泰姆	ArchiZSq嘉泰姆 tectuZSq嘉泰姆	PhaseZSq嘉泰姆	No.ofZSq嘉泰姆 PWMZSq嘉泰姆 OutputZSq嘉泰姆	Output ZSq嘉泰姆 CurrentZSq嘉泰姆 (A) ZSq嘉泰姆	InputZSq嘉泰姆 Voltage (V) ZSq嘉泰姆		ReferenceZSq嘉泰姆 VoltageZSq嘉泰姆 (V) ZSq嘉泰姆	Bias ZSq嘉泰姆 VoltageZSq嘉泰姆 (V) ZSq嘉泰姆	QuiescentZSq嘉泰姆 CurrentZSq嘉泰姆 (uA) ZSq嘉泰姆
Part_No ZSq嘉泰姆	Package ZSq嘉泰姆	ArchiZSq嘉泰姆 tectuZSq嘉泰姆	PhaseZSq嘉泰姆	No.ofZSq嘉泰姆 PWMZSq嘉泰姆 OutputZSq嘉泰姆	Output ZSq嘉泰姆 CurrentZSq嘉泰姆 (A) ZSq嘉泰姆	minZSq嘉泰姆	maxZSq嘉泰姆	ReferenceZSq嘉泰姆 VoltageZSq嘉泰姆 (V) ZSq嘉泰姆	Bias ZSq嘉泰姆 VoltageZSq嘉泰姆 (V) ZSq嘉泰姆	QuiescentZSq嘉泰姆 CurrentZSq嘉泰姆 (uA) ZSq嘉泰姆
CXSD6273ZSq嘉泰姆	SOP-14ZSq嘉泰姆 QSOP-16ZSq嘉泰姆 QFN4x4-16ZSq嘉泰姆	VM ZSq嘉泰姆	1 ZSq嘉泰姆	1 ZSq嘉泰姆	30ZSq嘉泰姆	2.9 ZSq嘉泰姆	13.2ZSq嘉泰姆	0.9ZSq嘉泰姆	12 ZSq嘉泰姆	8000ZSq嘉泰姆
CXSD6274ZSq嘉泰姆	SOP-8ZSq嘉泰姆	VM ZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	20ZSq嘉泰姆	2.9 ZSq嘉泰姆	13.2 ZSq嘉泰姆	0.8ZSq嘉泰姆	12ZSq嘉泰姆	5000ZSq嘉泰姆
CXSD6274CZSq嘉泰姆	SOP-8ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	20ZSq嘉泰姆	2.9ZSq嘉泰姆	13.2ZSq嘉泰姆	0.8ZSq嘉泰姆	12ZSq嘉泰姆	5000ZSq嘉泰姆
CXSD6275ZSq嘉泰姆	QFN4x4-24ZSq嘉泰姆	VMZSq嘉泰姆	2ZSq嘉泰姆	1ZSq嘉泰姆	60ZSq嘉泰姆	3.1ZSq嘉泰姆	13.2ZSq嘉泰姆	0.6ZSq嘉泰姆	12ZSq嘉泰姆	5000ZSq嘉泰姆
CXSD6276ZSq嘉泰姆	SOP-8ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	20ZSq嘉泰姆	2.2ZSq嘉泰姆	13.2ZSq嘉泰姆	0.8ZSq嘉泰姆	5~12ZSq嘉泰姆	2100ZSq嘉泰姆
CXSD6276AZSq嘉泰姆	SOP-8ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	20ZSq嘉泰姆	2.2ZSq嘉泰姆	13.2ZSq嘉泰姆	0.8ZSq嘉泰姆	5~12ZSq嘉泰姆	2100ZSq嘉泰姆
CXSD6277/A/BZSq嘉泰姆	SOP8\|TSSOP8ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	5ZSq嘉泰姆	5ZSq嘉泰姆	13.2ZSq嘉泰姆	1.25\|0.8ZSq嘉泰姆	5~12ZSq嘉泰姆	3000ZSq嘉泰姆
CXSD6278ZSq嘉泰姆	SOP-8ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	10ZSq嘉泰姆	3.3ZSq嘉泰姆	5.5ZSq嘉泰姆	0.8ZSq嘉泰姆	5ZSq嘉泰姆	2100ZSq嘉泰姆
CXSD6279BZSq嘉泰姆	SOP-14ZSq嘉泰姆	VM ZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	10ZSq嘉泰姆	5ZSq嘉泰姆	13.2ZSq嘉泰姆	0.8ZSq嘉泰姆	12ZSq嘉泰姆	2000ZSq嘉泰姆
CXSD6280ZSq嘉泰姆	TSSOP-24ZSq嘉泰姆 \|QFN5x5-32ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	2ZSq嘉泰姆	20ZSq嘉泰姆	5ZSq嘉泰姆	13.2ZSq嘉泰姆	0.6ZSq嘉泰姆	5~12ZSq嘉泰姆	4000ZSq嘉泰姆
CXSD6281NZSq嘉泰姆	SOP14ZSq嘉泰姆 QSOP16ZSq嘉泰姆 QFN-16ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	30ZSq嘉泰姆	2.9ZSq嘉泰姆	13.2ZSq嘉泰姆	0.9ZSq嘉泰姆	12ZSq嘉泰姆	4000ZSq嘉泰姆
CXSD6282ZSq嘉泰姆	SOP-14ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	30ZSq嘉泰姆	2.2ZSq嘉泰姆	13.2ZSq嘉泰姆	0.6ZSq嘉泰姆	12ZSq嘉泰姆	5000ZSq嘉泰姆
CXSD6282AZSq嘉泰姆	SOP-14ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	30ZSq嘉泰姆	2.2ZSq嘉泰姆	13.2ZSq嘉泰姆	0.6ZSq嘉泰姆	12ZSq嘉泰姆	5000ZSq嘉泰姆
CXSD6283ZSq嘉泰姆	SOP-14ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	1ZSq嘉泰姆	25ZSq嘉泰姆	2.2ZSq嘉泰姆	13.2ZSq嘉泰姆	0.8ZSq嘉泰姆	12ZSq嘉泰姆	5000ZSq嘉泰姆
CXSD6284/AZSq嘉泰姆	LQFP7x7 48ZSq嘉泰姆 TQFN7x7-48ZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	6ZSq嘉泰姆	0.015ZSq嘉泰姆	1.4ZSq嘉泰姆	6.5ZSq嘉泰姆	-ZSq嘉泰姆	5ZSq嘉泰姆	1800ZSq嘉泰姆
CXSD6285ZSq嘉泰姆	TSSOP-24PZSq嘉泰姆	VMZSq嘉泰姆	1ZSq嘉泰姆	2ZSq嘉泰姆	20ZSq嘉泰姆	2.97ZSq嘉泰姆	5.5ZSq嘉泰姆	0.8ZSq嘉泰姆	5~12ZSq嘉泰姆	5000ZSq嘉泰姆
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上一篇：两相电压模式和固定频率降压控制器CXSD62103从100kHz到800kHz的可编程脉宽调制开关频率无损耗低边MOSFET Ron电流传感

下一篇：电荷泵CXSD62105笔记本电脑的系统电源脉宽调制控制器集成了双降压恒时同步的脉宽调制控制器

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