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两个低电压降调节器CXSD62114双降压恒定时间同步PWM控制器内部转换MOSFET
发表时间:2020-04-23浏览次数:119
两个低电压降调节器CXSD62114双降压恒定时间同步PWM控制器内部转换MOSFET
 

目录WRj嘉泰姆

1.产品概述                       2.产品特点WRj嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 WRj嘉泰姆
5.产品封装图                     6.电路原理图                   WRj嘉泰姆
7.功能概述                        8.相关产品WRj嘉泰姆

一,产品概述(General Description)    WRj嘉泰姆


  The CXSD62114 integrates dual step-down, constant-on-time,WRj嘉泰姆

synchronous PWM controllers (that drives dual N-channel MOSFETs forWRj嘉泰姆
each channel) and two low drop-out regulators as well as various protectionsWRj嘉泰姆
into a chip.The PWM controllers step down high voltage of a batteryWRj嘉泰姆
to generate low-voltage for NB applications. The output of PWM1 andWRj嘉泰姆
PWM2 can be adjusted from 2V to 5.5V by setting a resistive voltage-dividerWRj嘉泰姆
from VOUTx to GND.The linear regulators provide 5V and 3.3V output forWRj嘉泰姆
standby power supply. The linear regulators provide up to 100mA outputWRj嘉泰姆
current. When the PWMx output voltage is higher than LDOx bypass threshold, the related LDOx regulator is shut off and its output is connected to VOUTxWRj嘉泰姆
by internal switchover MOSFET. It can save power dissipation. The chargeWRj嘉泰姆
pump circuit with 250kHz clock driver uses VOUT1 as its power supply to generate ap-proximately 15V DC voltage.WRj嘉泰姆
  The CXSD62114 provides excellent transient response and accurate DC output voltage in either PFM or PWM Mode. In Pulse-Frequency Mode (PFM),WRj嘉泰姆
the CXSD62114 provides very high efficiency over light to heavy loadsWRj嘉泰姆

with loading-modulated switching frequencies. The Forced-PWM Mode works nearly at constant frequency for low-noise requirements. The unique ultrasonicWRj嘉泰姆
mode maintains the switching frequency above 25kHz, which eliminates noise in audio application.The CXSD62114A/D has individual enable controls forWRj嘉泰姆
each PWM channels. Pulling both EN1/2 pin low shuts down the all of outputs unless LDO3 output. The LDO3 and LDO5 of CXSD62114B/C are always on standby power.The CXSD62114 is available in a TQFN3x3-20 package.WRj嘉泰姆
二.产品特点(Features)WRj嘉泰姆


Wide Input voltage Range from 5.5V to 25VWRj嘉泰姆
Provide 5 Independent Outputs with ±1.0% Accu-racy Over-TemperatureWRj嘉泰姆
PWM1 Controller with Adjustable (2V to 5.5V) Out-putWRj嘉泰姆
- PWM2 Controller with Adjustable (2V to 5.5V) Out-putWRj嘉泰姆
100mA Low Dropout Regulator (LDO5) with Fixed 5V OutputWRj嘉泰姆
- 100mA Low Dropout Regulator (LDO3) with Fixed 3.3V OutputWRj嘉泰姆
250kHz Clock Signal for 15V Charge Pump (Used PWM1 as Its Power Supply)WRj嘉泰姆
Excellent Line/Load Regulations about±1.5% overWRj嘉泰姆
temperature range at PWM ChannelsWRj嘉泰姆
Low Consumption in Standby ModeWRj嘉泰姆
2Cells Input Battery SupportWRj嘉泰姆
Built in POR Control Scheme ImplementedWRj嘉泰姆
Constant On-Time Control SchemeWRj嘉泰姆
Built in Soft Start for PWM Outputs and Soft StopWRj嘉泰姆
for PWM Outputs and LDO OutputsWRj嘉泰姆
Integrated Bootstrap Forward P-CH MOSFETWRj嘉泰姆
High Efficiency over Light to Full Load Range (PWMs)WRj嘉泰姆
Built in Power Good Indicators (PWMs)WRj嘉泰姆
60% Under-Voltage and 115% Over-Voltage Protec-tions (PWM)WRj嘉泰姆
Adjustable Current-Limit Protection (PWMs)WRj嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)WRj嘉泰姆
Over-Temperature ProtectionWRj嘉泰姆
3mmx3mm Thin QFN-20 (TQFN3x3-20) packageWRj嘉泰姆
Lead Free and Green Device Available (RoHS Compliant)WRj嘉泰姆
三,应用范围 (Applications)WRj嘉泰姆


Notebook and Sub-Notebook ComputersWRj嘉泰姆
Portable DevicesWRj嘉泰姆
DDR1, DDR2, and DDR3 Power SuppliesWRj嘉泰姆
3-Cell and 4-Cell Li+ Battery-Powered DevicesWRj嘉泰姆
Graphic CardsWRj嘉泰姆
Game ConsolesWRj嘉泰姆
TelecommunicationsWRj嘉泰姆
四.下载产品资料PDF文档 WRj嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持WRj嘉泰姆

 QQ截图20160419174301.jpgWRj嘉泰姆

五,产品封装图 (Package)WRj嘉泰姆


blob.pngWRj嘉泰姆
blob.pngWRj嘉泰姆

六.电路原理图WRj嘉泰姆


blob.pngWRj嘉泰姆

七,功能概述WRj嘉泰姆


the node.WRj嘉泰姆
Decoupling capacitor, the resistor dividers, boot capacitors, and current-limit stetting resistor shouldWRj嘉泰姆
be close to their pins. (For example, place the decoupling ceramic capacitor near the drain of theWRj嘉泰姆
high-side MOSFET as close as possible. The bulk capacitors are also placednear the drain).WRj嘉泰姆
The input capacitor should be near the drain of the upper MOSFET; the high quality ceramic decouplingWRj嘉泰姆
capacitor can be put close to the VCC and GND pins;the output capacitor should be near the loads. TheWRj嘉泰姆
input capacitor GND should be close to the output ca-pacitor GND and the lower MOSFET GND.WRj嘉泰姆
The drain of the MOSFETs (V IN and PHASEx nodes)should be a large plane for heat sinking. And PHASExWRj嘉泰姆
pin traces are also the return path for UGATEx. Con-nect these pins to the respective converter’s upperWRj嘉泰姆
MOSFET source.WRj嘉泰姆
The controller used ripple mode control. Build the re-sistor divider close to the FB1 pin so that the highWRj嘉泰姆
impedance trace is shorter when the output voltage is in ad justable mode. And the FB1 pin traces can’t beWRj嘉泰姆
close to the switching signal traces (UGATEx, LGATEx,BOOTx, and PHASEx).WRj嘉泰姆
The PGND trace should be a separate trace, and in-dependently go to the source of the low-side MOSFETsWRj嘉泰姆
for current-limit accuracy.WRj嘉泰姆
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1WRj嘉泰姆

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