The APL3222 ,APL3157advanced load management switch tar- gets applications requiring a highly integrated solution.

Features0mK嘉泰姆

Input Voltage Operating Range:1.5V to 5.5V0mK嘉泰姆

Typical RDS(ON)0mK嘉泰姆

– 21mΩ at VIN =5.5V0mK嘉泰姆

– 23mΩ at VIN =4.5V0mK嘉泰姆

– 41mΩ at VIN =1.8V0mK嘉泰姆

– 90mΩ at VIN =1.5V0mK嘉泰姆

Slew Rate/Inrush Control with t = 2.7ms(Typ)0mK嘉泰姆

R0mK嘉泰姆

3.5A Maximum Continuous Current Capability0mK嘉泰姆

Low Off Switch Current<1µA0mK嘉泰姆

True Reverse Current Blocking(TRCB)0mK嘉泰姆

Logic CMOS IO Meets JESD76 Standard for GPIO0mK嘉泰姆

Interface and Related Power Supply Require-0mK嘉泰姆

ments0mK嘉泰姆

ESD Protected0mK嘉泰姆

– Human Body Model >8kV0mK嘉泰姆

– Charged Device Model >1.5kV0mK嘉泰姆

– IEC 61000-4-2 Air Discharge >15kV0mK嘉泰姆

– IEC 61000-4-2 Contact Discharge >8kV0mK嘉泰姆

Tiny small WLCSP 1.2x0.8-6 Package0mK嘉泰姆

Lead Free and Green Devices Available (RoHS0mK嘉泰姆

Compliant)0mK嘉泰姆

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General Description0mK嘉泰姆

The APL3222 ,APL3157advanced load management switch tar-0mK嘉泰姆

gets applications requiring a highly integrated solution. It0mK嘉泰姆

disconnects loads powered from the DC power rail (<6V)0mK嘉泰姆

with stringent off-state current targets and high load ca-0mK嘉泰姆

pacitances (up to 100µF). The APL3222 consists of slew-0mK嘉泰姆

rate controlled low-impedance MOSFET switch (23mΩ0mK嘉泰姆

typical) and integrated analog features. The slew-rate0mK嘉泰姆

controlled turn-on characteristic prevents inrush current0mK嘉泰姆

and the resulting excessive voltage droop on power rails.0mK嘉泰姆

The APL3222 has a True Reverse Current Blocking0mK嘉泰姆

(TRCB) function that obstructs unwanted reverse current0mK嘉泰姆

from VOUT to VIN during both ON and OFF states.0mK嘉泰姆

The exceptionally low off-state current drain (<1µA0mK嘉泰姆

maximum) facilitates compliance with standby power0mK嘉泰姆

requirements. The input voltage range operates from0mK嘉泰姆

1.5V to 5.5VDC to support a wide range of applications in0mK嘉泰姆

consumer, optical, medical, storage, portable, and0mK嘉泰姆

industrial device power management. Switch control is0mK嘉泰姆

managed by a logic input (active HIGH) capable of inter-0mK嘉泰姆

facing directly with low-voltage control signal / General-0mK嘉泰姆

Purpose Input / Output (GPIO) without an external pull-0mK嘉泰姆

down resistor.0mK嘉泰姆

The device is packaged in advanced, fully “green”</span>0mK嘉泰姆

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Pin Configuration0mK嘉泰姆

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Top View0mK嘉泰姆

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compliant, 1.2mm x 0.8mm, Wafer-Level Chip-Scale Pack-0mK嘉泰姆

age (WLCSP) with backside lamination.0mK嘉泰姆

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