The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137-1) or five (CXSU63137-2)

发布时间:2020-04-06 09:43:38 浏览次数:703 作者:嘉泰姆 来源:1
摘要:The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137-1) or five (CXSU63137-2)

目录bpx嘉泰姆

1.产品概述                       2.产品特点
3.应用范围                       4.下载产品资料PDF文档 
5.产品封装图</span>                     6.电路原理图</span>                   
7.
功能概述
                        8.相关产品bpx嘉泰姆

一,产品概述(General Description)         bpx嘉泰姆


           The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.
      The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.
The amplifiers are ideal for VCOM and VGAMMA applications, with
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slew
rate. All inputs and outputs are rail-to-rail.
     The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).

二.产品特点(Features)bpx嘉泰姆


· 2.6V to 6.5V Input Supply Range bpx嘉泰姆

· Current-Mode Step-Up Regulator bpx嘉泰姆

 - Fast Transient Response bpx嘉泰姆

 - 1.2MHz Fixed Operating Frequency bpx嘉泰姆

· ±1.5% High-Accuracy Output Voltage bpx嘉泰姆

· 3A, 20V, 0.25W Internal N-Channel MOSFET bpx嘉泰姆

· High Efficiency bpx嘉泰姆

· Low Quiescent Current (0.6mA Typical) bpx嘉泰姆

· Linear-Regulator Controllers for VGON and VGOFF bpx嘉泰姆

· High-performance Operational Amplifiers bpx嘉泰姆

 - ±150mA Output Short-Circuit Currentbpx嘉泰姆

 - 13V/ms Slew Rate - 10MHz, -3dB Bandwidth bpx嘉泰姆

 - Rail-to-Rail Inputs/Outputs bpx嘉泰姆

· Fault-Delay Timer and Fault Latch for All Regulator Outputs bpx嘉泰姆

· Over-Temperature Protection bpx嘉泰姆

· Available in Compact 32-pin 5mmx5mm Thin QFN Package (TQFN5x5-32) bpx嘉泰姆

· Lead Free Available (RoHS Compliant)
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三</span>,应用范围 (Applications)bpx嘉泰姆


    TFT LCD Displays for Monitors
   TFT LCD Displays for Notebook Computers
   Automotive Displays

四.下载产品资料PDF文档 
bpx嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持</span>!</span>
bpx嘉泰姆

 QQ截图20160419174301.jpgbpx嘉泰姆

五,产品封装图 (Package)bpx嘉泰姆


blob.pngblob.pngPin Function Description
bpx嘉泰姆

Pinbpx嘉泰姆

Namebpx嘉泰姆

Function Descriptionbpx嘉泰姆

CXSU63137bpx嘉泰姆

CXSU63137-1bpx嘉泰姆

CXSU63137-2bpx嘉泰姆

1bpx嘉泰姆

SRCbpx嘉泰姆

SRCbpx嘉泰姆

SRCbpx嘉泰姆

Switch Input. Source of the internal high-voltage P-channel MOSFET. Bypass
SRC to PGND with a minimum of 0.1μF capacitor closed to the pins.bpx嘉泰姆

2bpx嘉泰姆

REFbpx嘉泰姆

REFbpx嘉泰姆

REFbpx嘉泰姆

Reference voltage output. Bypass REF to AGND with a minimum of
0.22μFcapacitor closed to the pins.bpx嘉泰姆

3bpx嘉泰姆

AGNDbpx嘉泰姆

AGNDbpx嘉泰姆

AGNDbpx嘉泰姆

Analog Ground for Step-Up Regulator and Linear Regulators. Connect to
power ground (PGND) underneath the IC.bpx嘉泰姆

4bpx嘉泰姆

PGNDbpx嘉泰姆

PGNDbpx嘉泰姆

PGNDbpx嘉泰姆

Power Ground for Step-Up Regulator. PGND is the source of the main step-up
n-channel power MOSFET. Connect PGND to the ground terminals of output
capacitors through a short, wide PC board trace. Connect to analog ground
(AGND) underneath the IC.bpx嘉泰姆

5bpx嘉泰姆

OUT1bpx嘉泰姆

OUT1bpx嘉泰姆

OUT1bpx嘉泰姆

Output of Operational-Amplifier 1bpx嘉泰姆

6bpx嘉泰姆

NEG1bpx嘉泰姆

NEG1bpx嘉泰姆

NEG1bpx嘉泰姆

Inverting Input of Operational-Amplifier 1bpx嘉泰姆

7bpx嘉泰姆

POS1bpx嘉泰姆

POS1bpx嘉泰姆

POS1bpx嘉泰姆

Non-inverting Input of Operational-Amplifier 1bpx嘉泰姆

8bpx嘉泰姆

NCbpx嘉泰姆

OUT2bpx嘉泰姆

OUT2bpx嘉泰姆

Output of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internal
connected of CXSU63137.bpx嘉泰姆

9bpx嘉泰姆

NCbpx嘉泰姆

NEG2bpx嘉泰姆

NEG2bpx嘉泰姆

Inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internal
connected of CXSU63137.bpx嘉泰姆

10bpx嘉泰姆

ICbpx嘉泰姆

POS2bpx嘉泰姆

POS2bpx嘉泰姆

Non-inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. Internal
connected to GND of CXSU63137bpx嘉泰姆

11bpx嘉泰姆

BGNDbpx嘉泰姆

BGNDbpx嘉泰姆

BGNDbpx嘉泰姆

Analog Ground for Operational Amplifiers. Connect to power ground (PGND)
underneath the IC.bpx嘉泰姆

12bpx嘉泰姆

NCbpx嘉泰姆

NCbpx嘉泰姆

POS3bpx嘉泰姆

Non-inverting Input of Operational-Amplifier 3 of CXSU63137. No internal
connected of CXSU63137/CXSU63137.bpx嘉泰姆

13bpx嘉泰姆

NCbpx嘉泰姆

NCbpx嘉泰姆

OUT3bpx嘉泰姆

Output of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.bpx嘉泰姆

14bpx嘉泰姆

SUPbpx嘉泰姆

SUPbpx嘉泰姆

SUPbpx嘉泰姆

Power Input of Operational Amplifiers. Typically connected to VMAIN. Bypass
SUP to BGND with a 0.1μF capacitor.bpx嘉泰姆

15bpx嘉泰姆

NCbpx嘉泰姆

POS3bpx嘉泰姆

POS4bpx嘉泰姆

Non-inverting Input of Operational-Amplifier 4 of CXSU63137. Non-inverting
Input of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137.bpx嘉泰姆

16bpx嘉泰姆

NCbpx嘉泰姆

NEG3bpx嘉泰姆

NEG4bpx嘉泰姆

Inverting Input of Operational-Amplifier 4 of CXSU63137. Inverting Input of
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.bpx嘉泰姆

17bpx嘉泰姆

NCbpx嘉泰姆

OUT3bpx嘉泰姆

OUT4bpx嘉泰姆

Output of Operational-Amplifier 4 of CXSU63137. Output of
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.bpx嘉泰姆

18bpx嘉泰姆

ICbpx嘉泰姆

ICbpx嘉泰姆

POS5bpx嘉泰姆

Non-inverting Input of Operational-Amplifier 5 of CXSU63137. Internal connected
to GND of CXSU63137/CXSU63137.bpx嘉泰姆

19bpx嘉泰姆

NCbpx嘉泰姆

NCbpx嘉泰姆

NEG5bpx嘉泰姆

Inverting Input of Operational-Amplifier 5 of CXSU63137. No internal connected
of CXSU63137/CXSU63137.bpx嘉泰姆

20bpx嘉泰姆

NCbpx嘉泰姆

NCbpx嘉泰姆

OUT5bpx嘉泰姆

Output of Operational-Amplifier 5 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.bpx嘉泰姆

21bpx嘉泰姆

LXbpx嘉泰姆

LXbpx嘉泰姆

LXbpx嘉泰姆

N-Channel Power MOSFET Drain and Switching Node. Connect the inductor
and Schottky diode to LX and minimize the trace area for lowest EMI.bpx嘉泰姆

22bpx嘉泰姆

INbpx嘉泰姆

INbpx嘉泰姆

INbpx嘉泰姆

Supply Voltage Input. Bypass IN to AGND with a 0.1μF capacitor. IN can range
from 2.6V to 6.5V.bpx嘉泰姆

23bpx嘉泰姆

FBbpx嘉泰姆

FBbpx嘉泰姆

FBbpx嘉泰姆

Step-Up Regulator Feedback Input. Connect a resistive voltage-divider from
the output (VMAIN) to FB to analog ground (AGND). Place the divider within
5mm of FB.bpx嘉泰姆

24bpx嘉泰姆

COMPbpx嘉泰姆

COMPbpx嘉泰姆

COMPbpx嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RC
from COMP to AGND.bpx嘉泰姆

PinFunction Description
bpx嘉泰姆

Pinbpx嘉泰姆

Namebpx嘉泰姆

Function Descriptionbpx嘉泰姆

CXSU63137bpx嘉泰姆

CXSU63137-1bpx嘉泰姆

CXSU63137-2bpx嘉泰姆

24bpx嘉泰姆

COMPbpx嘉泰姆

COMPbpx嘉泰姆

COMPbpx嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RC
from COMP to AGND.bpx嘉泰姆

25bpx嘉泰姆

FBPbpx嘉泰姆

FBPbpx嘉泰姆

FBPbpx嘉泰姆

Gate-On Linear-Regulator Feedback Input. Connect FBP to the center of a
resistive voltage-divider between the regulator output and AGND to set the
gate-on linear regulator output voltage. Place the resistive voltage-divider
close to the pin.bpx嘉泰姆

26bpx嘉泰姆

DRVPbpx嘉泰姆

DRVPbpx嘉泰姆

DRVPbpx嘉泰姆

Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channel
MOSFET. Connect DRVP to the base of an external PNP pass transistor.bpx嘉泰姆

27bpx嘉泰姆

FBNbpx嘉泰姆

FBNbpx嘉泰姆

FBNbpx嘉泰姆

Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of a
resistive voltage-divider between the regulator output and REF to set the
gate-off linear regulator output voltage. Place the resistive voltage-divider
close to the pin.bpx嘉泰姆

28bpx嘉泰姆

DRVNbpx嘉泰姆

DRVNbpx嘉泰姆

DRVNbpx嘉泰姆

Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channel
MOSFET. Connect DRVN to the base of an external NPN pass transistor.bpx嘉泰姆

29bpx嘉泰姆

DELbpx嘉泰姆

DELbpx嘉泰姆

DELbpx嘉泰姆

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to
set the high-voltage switch startup delay.bpx嘉泰姆

30bpx嘉泰姆

CTLbpx嘉泰姆

CTLbpx嘉泰姆

CTLbpx嘉泰姆

High-Voltage Switch Control Input. When CTL is high, the high-voltage switch
between COM and SRC is on and the high-voltage switch between COM and
DRN is off. When CTL is low, the high-voltage switch between COM and SRC
is off and the high-voltage switch between COM and DRN is on. CTL is
inhibited by the undervoltage lockout and when the voltage on DEL is less than
1.25V.bpx嘉泰姆

31bpx嘉泰姆

DRNbpx嘉泰姆

DRNbpx嘉泰姆

DRNbpx嘉泰姆

Switch Input. Drain of the internal high-voltage back-to-back P-channel
MOSFETs connected to COM. Do not allows the voltage on DRN to exceed
VSRC.bpx嘉泰姆

32bpx嘉泰姆

COMbpx嘉泰姆

COMbpx嘉泰姆

COMbpx嘉泰姆

Internal High-Voltage MOSFET Switch Common Terminal. Do not allow the
voltage on COM to exceed VSRC.bpx嘉泰姆

六.电路原理图</span>bpx嘉泰姆




七</span>,功能概述
For all switching power supplies, the layout is an impor-tant step in the design; especially at high peak currents and switching frequencies. There are some general guidelines for layout:
1.Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device.Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.
2.Place the REF and IN bypass capacitors close to the pins. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace.
3.Create a power ground (PGND) and a signal ground island and connect at only one point. The power ground consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maxi-mizing the width of the power ground traces im-proves efficiency and reduces output voltage ripple and noise spikes. The analog ground plane (AGND) consisting of the AGND pin, all the feed-back-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes.
4.The feedback network should sense the output volt-age directly from the point of load, and be as far away from LX node as possible.
5.The exposed die plate, underneath the package,should be soldered to an equivalent area of metal on the PCB. This contact area should have mul-tiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.
6.To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bot-tom and top PCB areas especially should be maxi-mized to allow thermal dissipation to the surround-ing air.
7.Minimize feedback input track lengths to avoid switching noise pick-up
八,相关产品
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Switching Regulator > Boost Converterbpx嘉泰姆

 Part_No bpx嘉泰姆

Packagebpx嘉泰姆

Archi-tecture bpx嘉泰姆

Input bpx嘉泰姆

Voltage    bpx嘉泰姆

Max Adj.bpx嘉泰姆

Output bpx嘉泰姆

Voltage bpx嘉泰姆

Switch Current Limit (max) bpx嘉泰姆

Fixed bpx嘉泰姆

Output bpx嘉泰姆

Voltage  bpx嘉泰姆

Switching bpx嘉泰姆

Frequency bpx嘉泰姆

Internal Power   Switch bpx嘉泰姆

Sync. Rectifier bpx嘉泰姆


minbpx嘉泰姆

maxbpx嘉泰姆

minbpx嘉泰姆

maxbpx嘉泰姆

(A)bpx嘉泰姆

(V)bpx嘉泰姆

(kHz)bpx嘉泰姆


CXSU63133bpx嘉泰姆

SOT89bpx嘉泰姆

VM bpx嘉泰姆

0.9bpx嘉泰姆

5.5bpx嘉泰姆

2.5bpx嘉泰姆

5.5bpx嘉泰姆

0.5bpx嘉泰姆

1.8|2.6|2.8|3bpx嘉泰姆

|3.3|3.8|4.5|5bpx嘉泰姆

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200 ~ 1000bpx嘉泰姆

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TSSOP8|SOP-8Pbpx嘉泰姆

VMbpx嘉泰姆

1bpx嘉泰姆

5.5bpx嘉泰姆

2.5bpx嘉泰姆

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6.5bpx嘉泰姆

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