CXDR75107 An internal timer delays the return of the output to the inactive state to ensure proper system reset. The delay time, td, starts after VCC has risen above the threshold voltage VIT+. When t

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An internal timer delays the return of the output to the inactive state to ensure proper system reset. The delay time, td, starts after VCC has risen above the threshold voltage VIT+. When the supply voltage drops below the threshold voltage VIT- (2), the outputs becomes active again. No external components are required. All the devices have a fixed-sense threshold voltage VIT- set by an internal voltage divider. The CXDR75107 incorporate a manual reset input MR . A low level at MR causes RESET (RESET) to become active. The product spectrum is designed for supply voltages of 2.5V, 3V, 3.3V, and 5V. The circuits are available in a SOT-23-5 package The CXDR75107 provide circuits initialization and timing supervision, primarily for DSP and processor-based systems. During power-on, RESET (RESET) is asserted when supply voltage VCC becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors VCC and keeps RESET (RESET) active as long as VCC remains below the threshold voltage

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„ Power-On Reset Generator With Fixed Delay Time of 200ms Euw嘉泰姆

„ Manual Reset Input Euw嘉泰姆

„ Push-Pull RESET and RESET Output Euw嘉泰姆

„ Supply Voltage Supervision Range 2.5V, 3V, 3.3V, 5V Euw嘉泰姆

„ Supply Current of 10μA at VCC=3.3V Euw嘉泰姆

„ SOT-23-5 PackageEuw嘉泰姆

   应用范围 返回TOPEuw嘉泰姆

„ Critical μP and μC Power Monitoring Euw嘉泰姆

„ Industrial Equipment Euw嘉泰姆

„ Programmable Controls Euw嘉泰姆

„ Automotive Systems Euw嘉泰姆

„ Portable/Battery-Powered Equipment Euw嘉泰姆

„ Intelligent Instruments Euw嘉泰姆

„ Wireless Communications Systems Euw嘉泰姆

„ Notebook/Desktop ComputersEuw嘉泰姆

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