CXSD62102A is a single-phase, constant on-time,synchronous PWM controller, which drives N-channel MOSFETs. CXSD62102A steps down high voltage to generate low-voltage chipset or RAM supplies in not

发布时间：2020-04-06 09:43:38 浏览次数：702 作者：嘉泰姆来源：1

摘要：CXSD62102A is a single-phase, constant on-time,synchronous PWM controller, which drives N-channel MOSFETs. CXSD62102A steps down high voltage to generate low-voltage chipset or RAM supplies in not

目录p8a嘉泰姆

1.产品概述 2.产品特点
3.应用范围 4.下载产品资料PDF文档
5.产品封装图 6.电路原理图
7.功能概述 8.相关产品p8a嘉泰姆

一,产品概述(General Description) p8a嘉泰姆

The CXSD62102A is a single-phase, constant on-time,synchronous PWM controller, which drives N-channel MOSFETs. The CXSD62102A steps down high voltage to generate low-voltage chipset or RAM supplies in notebook computers.
The CXSD62102A provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode.In Pulse Frequency Mode (PFM), the CXSD62102A provides very high efficiency over light to heavy loads with loading-
modulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise requirements.
The CXSD62102A is equipped with accurate positive current limit, output under-voltage, and output over-voltage protections, perfect for NB applications. The Power-On-Reset function monitors the voltage on VCC to prevent wrong operation during power-on. The CXSD62102A has a 1ms digital soft start and built-in an integrated output discharge device for soft stop. An internal integrated soft-
start ramps up the output voltage with programmable slew rate to reduce the start-up current. A soft-stop function actively discharges the output capacitors.
The CXSD62102A is available in 16pin TQFN3x3-16 package respectively.
二.产品特点(Features)p8a嘉泰姆

Adjustable Output Voltage from +0.6V to +3.3V
- 0.6V Reference Voltage
- ±0.6% Accuracy Over-Temperature
Operates from An Input Battery Voltage Range of
+1.8V to +28V
REFIN Function for Over-clocking Purpose from
0.5V~2.5V range
Power-On-Reset Monitoring on VCC pin
Excellent line and load transient responses
PFM mode for increased light load efficiency
Programmable PWM Frequency from 100kHz to 500kHz
Built in 30A Output current driving capability
Integrate MOSFET Drivers
Integrated Bootstrap Forward P-CH MOSFET
Power Good Monitoring
70% Under-Voltage Protection
125% Over-Voltage Protection
TQFN3x3-16 Package
Lead Free and Green Devices Available (RoHS Compliant)
三,应用范围 (Applications)p8a嘉泰姆

Notebook
Table PC
Hand-Held Portable
AIO PC
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四.下载产品资料PDF文档 p8a嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！
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QQ截图20160419174301.jpg p8a嘉泰姆

五,产品封装图 (Package)p8a嘉泰姆

p8a嘉泰姆

六.电路原理图p8a嘉泰姆

p8a嘉泰姆

七,功能概述p8a嘉泰姆

Input Capacitor Selection (Cont.)
higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current.
For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected be-
tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout.
MOSFET Selection
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:
For the low-side MOSFET, before it is turned on, the body diode has been conducting. The low-side MOSFET driver
will not charge the miller capacitor of this MOSFET.In the turning off process of the low-side MOSFET, the
load current will shift to the body diode first. The high dv/dt of the phase node voltage will charge the miller capaci-
tor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the low-
side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side MOSFET
will conduct most of the switching cycle; therefore, when using smaller RDS(ON) of the low-side MOSFET, the con-
verter can reduce power loss. The gate charge for this MOSFET is usually the secondary consideration. The
high-side MOSFET does not have this zero voltage switch-ing condition; in addition, it conducts for less time com-
pared to the low-side MOSFET, so the switching loss tends to be dominant. Priority should be given to the
MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.
The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capaci-
tance (CRSS) and maximum output current requirement.The losses in the MOSFETs have two components:
conduction loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately
given by the following equations:
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
Where TC is the temperature dependency of RDS(ON)FSW is the switching frequency
tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transition loss. The switching interval, tSW, is the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET.
Layout Consideration
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect- ing impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept sepa- rating and finally combined using ground plane construc-
tion or single point grounding. The best tie-point between the signal ground and the power ground is at the nega-
tive side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:· Keep the switching nodes (UGATE, LGATE, BOOT,
and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as
side MOSFET. On the other hand, the PGND trace should be a separate trace and independently go to
the source of the low-side MOSFET. Besides, the cur-rent sense resistor should be close to OCSET pin to
avoid parasitic capacitor effect and noise coupling.
· Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example,
place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.)
· The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capaci-
tors should be close to the loads. The input capaci-tor’s ground should be close to the grounds of the
output capacitors and low-side MOSFET.
· Locate the resistor-divider close to the FB pin to mini-mize the high impedance trace. In addition, FB pin
traces can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE).p8a嘉泰姆

Layout Consideration (Cont.)
p8a嘉泰姆

possible and there should be no other weak signal traces in parallel with theses traces on any layer.
· The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and
discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short
and wide.
· Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce of
the drain of the MOSFETs (VIN and PHASE nodes) can get better heat sinking.p8a嘉泰姆

· The PGND is the current sensing circuit reference ground and also the power ground of the LGATE low-p8a嘉泰姆

CXSD62102ACXSD62102Ap8a嘉泰姆

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CXSD62100p8a嘉泰姆	TQFN3x3-10p8a嘉泰姆	VMp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	25p8a嘉泰姆	4.5p8a嘉泰姆	13.2p8a嘉泰姆	0.6p8a嘉泰姆	5~12p8a嘉泰姆	2500p8a嘉泰姆
CXSD62101\|Lp8a嘉泰姆	TDFN3x3-10p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	30p8a嘉泰姆	3p8a嘉泰姆	25p8a嘉泰姆	0.8p8a嘉泰姆	5~12p8a嘉泰姆	2000p8a嘉泰姆
CXSD62102p8a嘉泰姆	TQFN3x3-16p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	30p8a嘉泰姆	1.8p8a嘉泰姆	28p8a嘉泰姆	0.6p8a嘉泰姆	5p8a嘉泰姆	600p8a嘉泰姆
CXSD62102Ap8a嘉泰姆	TQFN 3x3 16p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	30p8a嘉泰姆	1.8p8a嘉泰姆	28p8a嘉泰姆	0.6p8a嘉泰姆	5p8a嘉泰姆	600p8a嘉泰姆
CXSD62103p8a嘉泰姆	QFN4x4-24p8a嘉泰姆	VMp8a嘉泰姆	2p8a嘉泰姆	1p8a嘉泰姆	50p8a嘉泰姆	4.5p8a嘉泰姆	13.2p8a嘉泰姆	0.6p8a嘉泰姆	5~12p8a嘉泰姆	5000p8a嘉泰姆
CXSD62104p8a嘉泰姆	TQFN4x4-24p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	15p8a嘉泰姆	6p8a嘉泰姆	25p8a嘉泰姆	2p8a嘉泰姆	Np8a嘉泰姆	550p8a嘉泰姆
CXSD62105p8a嘉泰姆	TQFN4x4-24p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	15p8a嘉泰姆	6p8a嘉泰姆	25p8a嘉泰姆	2p8a嘉泰姆	Np8a嘉泰姆	550p8a嘉泰姆
CXSD62106\|Ap8a嘉泰姆	TQFN4x4-4p8a嘉泰姆 TQFN3x3-20p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	20p8a嘉泰姆	3p8a嘉泰姆	28p8a嘉泰姆	0.75p8a嘉泰姆	5p8a嘉泰姆	800p8a嘉泰姆
CXSD62107p8a嘉泰姆	TQFN3x3-16p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	20p8a嘉泰姆	1.8p8a嘉泰姆	28p8a嘉泰姆	0.75p8a嘉泰姆	5p8a嘉泰姆	400p8a嘉泰姆
CXSD62108p8a嘉泰姆	QFN3.5x3.5-14p8a嘉泰姆 TQFN3x3-16p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	20p8a嘉泰姆	1.8p8a嘉泰姆	28p8a嘉泰姆	0.75p8a嘉泰姆	5p8a嘉泰姆	400p8a嘉泰姆
CXSD62109p8a嘉泰姆	TQFN3x3-16p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	20p8a嘉泰姆	1.8p8a嘉泰姆	28p8a嘉泰姆	0.75p8a嘉泰姆	5p8a嘉泰姆	400p8a嘉泰姆
CXSD62110p8a嘉泰姆	QFN3x3-20p8a嘉泰姆 TQFN3x3-16p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	20p8a嘉泰姆	3p8a嘉泰姆	28p8a嘉泰姆	1.8\|1.5\|0.5p8a嘉泰姆	5p8a嘉泰姆	740p8a嘉泰姆
CXSD62111p8a嘉泰姆	TQFN4x4-24p8a嘉泰姆 \|QFN3x3-20p8a嘉泰姆	CMp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	15p8a嘉泰姆	5p8a嘉泰姆	28p8a嘉泰姆	0.5p8a嘉泰姆	Np8a嘉泰姆	3000p8a嘉泰姆
CXSD62112p8a嘉泰姆	TDFN3x3-10p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	20p8a嘉泰姆	1.8p8a嘉泰姆	28p8a嘉泰姆	0.5p8a嘉泰姆	5p8a嘉泰姆	250p8a嘉泰姆
CXSD62113\|Cp8a嘉泰姆	TQFN3x3-20p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	15p8a嘉泰姆	6p8a嘉泰姆	25p8a嘉泰姆	2p8a嘉泰姆	Np8a嘉泰姆	550p8a嘉泰姆
CXSD62113Ep8a嘉泰姆	TQFN 3x3 20p8a嘉泰姆	COTp8a嘉泰姆	2p8a嘉泰姆	2p8a嘉泰姆	11p8a嘉泰姆	6p8a嘉泰姆	25p8a嘉泰姆	2p8a嘉泰姆	Np8a嘉泰姆	550p8a嘉泰姆
CXSD62114p8a嘉泰姆	TQFN3x3-20p8a嘉泰姆	COTp8a嘉泰姆	2p8a嘉泰姆	2p8a嘉泰姆	11p8a嘉泰姆	5.5p8a嘉泰姆	25p8a嘉泰姆	2p8a嘉泰姆	Np8a嘉泰姆	280p8a嘉泰姆
CXSD62115p8a嘉泰姆	QFN4x4-24p8a嘉泰姆	VMp8a嘉泰姆	2p8a嘉泰姆	1p8a嘉泰姆	60p8a嘉泰姆	3.1p8a嘉泰姆	13.2p8a嘉泰姆	0.85p8a嘉泰姆	12p8a嘉泰姆	5000p8a嘉泰姆
CXSD62116A\|B\|Cp8a嘉泰姆	SOP-8Pp8a嘉泰姆	VMp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	20p8a嘉泰姆	2.9p8a嘉泰姆	13.2p8a嘉泰姆	0.8p8a嘉泰姆	12p8a嘉泰姆	16000p8a嘉泰姆
CXSD62117p8a嘉泰姆	SOP-20p8a嘉泰姆	VMp8a嘉泰姆	2p8a嘉泰姆	2p8a嘉泰姆	30p8a嘉泰姆	10p8a嘉泰姆	13.2p8a嘉泰姆	1p8a嘉泰姆	12p8a嘉泰姆	5000p8a嘉泰姆
CXSD62118p8a嘉泰姆	TDFN3x3-10p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	1p8a嘉泰姆	25p8a嘉泰姆	1.8p8a嘉泰姆	28p8a嘉泰姆	0.7p8a嘉泰姆	5p8a嘉泰姆	250p8a嘉泰姆
CXSD62119p8a嘉泰姆	TQFN3x3-20p8a嘉泰姆	COTp8a嘉泰姆	2p8a嘉泰姆	1p8a嘉泰姆	40p8a嘉泰姆	1.8p8a嘉泰姆	25p8a嘉泰姆	REFIN Settingp8a嘉泰姆	5p8a嘉泰姆	700p8a嘉泰姆
CXSD62120p8a嘉泰姆	QFN 3x3 20p8a嘉泰姆 TQFN 3x3 16p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	20p8a嘉泰姆	3p8a嘉泰姆	28p8a嘉泰姆	1.8\|1.5 1.35\|1.2 0.5p8a嘉泰姆	5p8a嘉泰姆	800p8a嘉泰姆
CXSD62121Ap8a嘉泰姆	TQFN3x3 20p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	15p8a嘉泰姆	3p8a嘉泰姆	28p8a嘉泰姆	0.75p8a嘉泰姆	5p8a嘉泰姆	220p8a嘉泰姆
CXSD62121Bp8a嘉泰姆	TQFN3x3 20p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	15p8a嘉泰姆	3p8a嘉泰姆	28p8a嘉泰姆	0.75p8a嘉泰姆	5p8a嘉泰姆	220p8a嘉泰姆
CXSD62121p8a嘉泰姆	TQFN3x3-20p8a嘉泰姆	COTp8a嘉泰姆	1p8a嘉泰姆	2p8a嘉泰姆	20p8a嘉泰姆	3p8a嘉泰姆	28p8a嘉泰姆	0.75p8a嘉泰姆	5p8a嘉泰姆	180p8a嘉泰姆

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CXSD62102A is a single-phase, constant on-time,synchronous PWM controller, which drives N-channel MOSFETs. CXSD62102A steps down high voltage to generate low-voltage chipset or RAM supplies in not

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CXSD62102A is a single-phase, constant on-time,synchronous PWM controller, which drives N-channel MOSFETs. CXSD62102A steps down high voltage to generate low-voltage chipset or RAM supplies in not

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