The CXSD62106/A integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It provides a complete power supply for DDR2 and DDR3 memory

发布时间:2020-04-06 09:43:38 浏览次数:703 作者:嘉泰姆 来源:1
摘要:The CXSD62106/A integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It provides a complete power supply for DDR2 and DDR3 memory

目录xWc嘉泰姆

1.产品概述                       2.产品特点
3.应用范围                       4.下载产品资料PDF文档 
5.产品封装图</span>                     6.电路原理图</span>                   
7.
功能概述
                        8.相关产品xWc嘉泰姆

,产品概述(General Description)         
      The CXSD62106/A integrates a synchronous buck PWM controller to generate
VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It provides
a complete power supply for DDR2 and DDR3 memory system. It offers the lowest
total solution cost in system where space is at a premium.
      The CXSD62106/A provides excellent transient response  and accurate DC 
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voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the CXSD62106/A provides very high efficiency over light to heavy loads with loading-modulated switching frequencies. On TQFN4x4- 24A package, the Forced PWM xWc嘉泰姆

Mode works nearly at con-stant frequency for low-noise requirements.
The CXSD62106/A is equipped with accurate current-limit,output under-voltage,
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and output over-voltage protections.A Power-On-Reset function monitors the xWc嘉泰姆

voltage on VCC prevents wrong operation during power on.The LDO is designed xWc嘉泰姆

to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination.The device integrates two power transistors to source or sink current xWc嘉泰姆

up to 1.5A. It also incorporates current-limit and thermal shutdown protection.xWc嘉泰姆

The output voltage of LDO tracks the voltage at VTTREF pin. An internal resistorxWc嘉泰姆

divider is used to provide a half voltage of VDDQ for VTTREF and VTT Voltage. xWc嘉泰姆

The VTT output voltage is only requiring 20μF of ceramic output capacitance forxWc嘉泰姆

 stability and fast transient response. The S3 and S5 pins provide the sleep statexWc嘉泰姆

 for VTT (S3 state)and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for VTT and VTTREF.
The CXSD62106/A is available in 4mmx4mm 24-pin TQFN package, and the 
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CXSD62106A is available in 3mmx3mm 20-pin TQFN package.
二</span>.产品特点(Features)
Buck Controller (VDDQ)
·  High Input Voltages Range from 3V to 28V Input Power
Provide 1.8V (DDR2), 1.5V (DDR3) or Adjustable
Output Voltage from 0.75V to 5.5V
- ±1% Accuracy Over-Temperature
Integrated MOSFET Drivers and Bootstrap Diode
Excellent Line and Load Transient Responses
PFM Mode for Increased Light Load Efficiency
Constant-On-Time Controller Scheme
- Switching Frequency Compensation for PWMMode
- Adjustable Switching Frequency from 100kHz
to 550kHz in PWM Mode with DC Output Current
Integrated MOSFET Drivers and Bootstrap Diode
S3 and S5 Pins Control The Device in S0, S3, or S4/S5 State
Power Good Monitoring
70% Under-Voltage Protection (UVP)
125% Over-Voltage Protection (OVP)
Adjustable Current-Limit Protection
Using Sense Low-Side MOSFET RDS(ON)
±1.5A LDO Section (VTT)
Souring or Sinking Current up to 1.5A
Fast Transient Response for Output Voltage
Output Ceramic Capacitors Support at Least 10μF MLCC
VTT and VTTREF Track at Half the VDDQSNS by Internal Divider
±20mV Accuracy for VTT and VTTREF
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Independent Over-Current-Limit (OCL) xWc嘉泰姆

Thermal Shutdown ProtectionxWc嘉泰姆

QFN-24 4mmx4mm Thin Package (TQFN4x4-24A)
for CXSD62106 and QFN-20 3mmx3mm Thin
Package (TQFN3x3-20) for CXSD62106A
Lead Free and Green Devices Available
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三</span>,应用范围 (Applications)xWc嘉泰姆


DDR2, and DDR3 Memory Power Supplies
SSTL-2 SSTL-18 and HSTL Termination

四.下载产品资料PDF文档 
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需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持</span>!</span>
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 QQ截图20160419174301.jpgxWc嘉泰姆

五,产品封装图 (Package)xWc嘉泰姆


blob.pngblob.pngxWc嘉泰姆

六.电路原理图</span>xWc嘉泰姆


blob.pngxWc嘉泰姆

七</span>,功能概述xWc嘉泰姆


Layout Consideration (Cont.)xWc嘉泰姆

· Keep the switching nodes (UGATE, LGATE, BOOT, and PHASE) away from sensitive small signal nodes
(VDDQSET, VTTREF, CS, and MODE) since these nodes are fast mov ing signals. Therefore, keep traces
to these nodes as short as possible and there should be no other weak signal traces in parallel with theses
traces on any layer.
 The signals going through theses traces have both high dv/dt and high di/dt, with high peak charging and
discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short
and wide.
Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Mini-
mizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.
ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are
also placednear the drain).
The input capacitor should be near the drain of the up per MOSFET; the high quality ceramic decoupling ca-
pacitor can be put close to the VCC and GND pins; the VTTREF decoupling capasitor should be close to the
VTTREF pin and GND; the VDDQ and VTT output ca-pacitors should be located right across their output pin
as clase as possible to the part to minimize parasitics.
The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND.
· The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking. And PHASE
pin traces are also the return path for UGATE. Connect this pin to the converter’s upper MOSFET source.
· The CXSD62106/A used ripple mode control. Build the resistor divider close to the VDDQSET pin so that the
high imped ance trace is shorter when the output volt-age is in ad justable mode. And the VDDQSET pin
traces can’t be closed to the switching signal traces (UGATE, LGATE, BOOT, and PHASE)
 The PGND trace should be a separate trace, and inde pendently go to the source of the low-side MOSFETs
for current limit accuracy.Decoupling capacitor, the resistor dividers, boot capacitors, and current limit stetting resistor should be close their pins. (For example, place the decouplingxWc嘉泰姆

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TQFN 3x3 16xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

1xWc嘉泰姆

30xWc嘉泰姆

1.8xWc嘉泰姆

28xWc嘉泰姆

0.6xWc嘉泰姆

5xWc嘉泰姆

600xWc嘉泰姆

CXSD62103xWc嘉泰姆

QFN4x4-24xWc嘉泰姆

VMxWc嘉泰姆

2xWc嘉泰姆

1xWc嘉泰姆

50xWc嘉泰姆

4.5xWc嘉泰姆

13.2xWc嘉泰姆

0.6xWc嘉泰姆

5~12xWc嘉泰姆

5000xWc嘉泰姆

CXSD62104xWc嘉泰姆

TQFN4x4-24xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

15xWc嘉泰姆

6xWc嘉泰姆

25xWc嘉泰姆

2xWc嘉泰姆

NxWc嘉泰姆

550xWc嘉泰姆

CXSD62105xWc嘉泰姆

TQFN4x4-24xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

15xWc嘉泰姆

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25xWc嘉泰姆

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550xWc嘉泰姆

CXSD62106|AxWc嘉泰姆

TQFN4x4-4xWc嘉泰姆

TQFN3x3-20xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

20xWc嘉泰姆

3xWc嘉泰姆

28xWc嘉泰姆

0.75xWc嘉泰姆

5xWc嘉泰姆

800xWc嘉泰姆

CXSD62107xWc嘉泰姆

TQFN3x3-16xWc嘉泰姆

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1xWc嘉泰姆

20xWc嘉泰姆

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28xWc嘉泰姆

0.75xWc嘉泰姆

5xWc嘉泰姆

400xWc嘉泰姆

CXSD62108xWc嘉泰姆

QFN3.5x3.5-14xWc嘉泰姆

TQFN3x3-16xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

1xWc嘉泰姆

20xWc嘉泰姆

1.8xWc嘉泰姆

28xWc嘉泰姆

0.75xWc嘉泰姆

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400xWc嘉泰姆

CXSD62109xWc嘉泰姆

TQFN3x3-16xWc嘉泰姆

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2xWc嘉泰姆

20xWc嘉泰姆

1.8xWc嘉泰姆

28xWc嘉泰姆

0.75xWc嘉泰姆

5xWc嘉泰姆

400xWc嘉泰姆

CXSD62110xWc嘉泰姆

QFN3x3-20xWc嘉泰姆

TQFN3x3-16xWc嘉泰姆

COTxWc嘉泰姆

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2xWc嘉泰姆

20xWc嘉泰姆

3xWc嘉泰姆

28xWc嘉泰姆

1.8|1.5|0.5xWc嘉泰姆

5xWc嘉泰姆

740xWc嘉泰姆

CXSD62111xWc嘉泰姆

TQFN4x4-24xWc嘉泰姆

|QFN3x3-20xWc嘉泰姆

CMxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

15xWc嘉泰姆

5xWc嘉泰姆

28xWc嘉泰姆

0.5xWc嘉泰姆

NxWc嘉泰姆

3000xWc嘉泰姆

CXSD62112xWc嘉泰姆

TDFN3x3-10xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

1xWc嘉泰姆

20xWc嘉泰姆

1.8xWc嘉泰姆

28xWc嘉泰姆

0.5xWc嘉泰姆

5xWc嘉泰姆

250xWc嘉泰姆

CXSD62113|CxWc嘉泰姆

TQFN3x3-20xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

15xWc嘉泰姆

6xWc嘉泰姆

25xWc嘉泰姆

2xWc嘉泰姆

NxWc嘉泰姆

550xWc嘉泰姆

CXSD62113ExWc嘉泰姆

TQFN 3x3 20xWc嘉泰姆

COTxWc嘉泰姆

2xWc嘉泰姆

2xWc嘉泰姆

11xWc嘉泰姆

6xWc嘉泰姆

25xWc嘉泰姆

2xWc嘉泰姆

NxWc嘉泰姆

550xWc嘉泰姆

CXSD62114xWc嘉泰姆

TQFN3x3-20xWc嘉泰姆

COTxWc嘉泰姆

2xWc嘉泰姆

2xWc嘉泰姆

11xWc嘉泰姆

5.5xWc嘉泰姆

25xWc嘉泰姆

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NxWc嘉泰姆

280xWc嘉泰姆

CXSD62115xWc嘉泰姆

QFN4x4-24xWc嘉泰姆

VMxWc嘉泰姆

2xWc嘉泰姆

1xWc嘉泰姆

60xWc嘉泰姆

3.1xWc嘉泰姆

13.2xWc嘉泰姆

0.85xWc嘉泰姆

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5000xWc嘉泰姆

CXSD62116A|B|CxWc嘉泰姆

SOP-8PxWc嘉泰姆

VMxWc嘉泰姆

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1xWc嘉泰姆

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2.9xWc嘉泰姆

13.2xWc嘉泰姆

0.8xWc嘉泰姆

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16000xWc嘉泰姆

CXSD62117xWc嘉泰姆

SOP-20xWc嘉泰姆

VMxWc嘉泰姆

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13.2xWc嘉泰姆

1xWc嘉泰姆

12xWc嘉泰姆

5000xWc嘉泰姆

CXSD62118xWc嘉泰姆

TDFN3x3-10xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

1xWc嘉泰姆

25xWc嘉泰姆

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28xWc嘉泰姆

0.7xWc嘉泰姆

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250xWc嘉泰姆

CXSD62119xWc嘉泰姆

TQFN3x3-20xWc嘉泰姆

COTxWc嘉泰姆

2xWc嘉泰姆

1xWc嘉泰姆

40xWc嘉泰姆

1.8xWc嘉泰姆

25xWc嘉泰姆

REFIN SettingxWc嘉泰姆

5xWc嘉泰姆

700xWc嘉泰姆

CXSD62120xWc嘉泰姆

QFN 3x3 20xWc嘉泰姆

TQFN 3x3 16xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

20xWc嘉泰姆

3xWc嘉泰姆

28xWc嘉泰姆

1.8|1.5 1.35|1.2 0.5xWc嘉泰姆

5xWc嘉泰姆

800xWc嘉泰姆

CXSD62121AxWc嘉泰姆

TQFN3x3 20xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

15xWc嘉泰姆

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28xWc嘉泰姆

0.75xWc嘉泰姆

5xWc嘉泰姆

220xWc嘉泰姆

CXSD62121BxWc嘉泰姆

TQFN3x3 20xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

15xWc嘉泰姆

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28xWc嘉泰姆

0.75xWc嘉泰姆

5xWc嘉泰姆

220xWc嘉泰姆

CXSD62121xWc嘉泰姆

TQFN3x3-20xWc嘉泰姆

COTxWc嘉泰姆

1xWc嘉泰姆

2xWc嘉泰姆

20xWc嘉泰姆

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0.75xWc嘉泰姆

5xWc嘉泰姆

180xWc嘉泰姆


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