The JTMA8828 is a single-phase, constant-on-time,synchronous(2)

　　七,功能概述
Input Capacitor Selection (Cont.)
higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current.
For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected be-
tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout

MOSFET Selection
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:
For the low-side MOSFET, before it is turned on, the body diode has been conducting. The low-side MOSFET driver
will not charge the miller capacitor of this MOSFET.In the turning off process of the low-side MOSFET, the
load current will shift to the body diode first. The high dv/dt of the phase node voltage will charge the miller capaci-
tor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the low-
side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side MOSFET
will conduct most of the switching cycle; therefore, when using smaller RDS(ON) of the low-side MOSFET, the con-
verter can reduce power loss. The gate charge for this MOSFET is usually the secondary consideration. The
high-side MOSFET does not have this zero voltage switch- ing condition; in addition, because it conducts for less
time compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be given to the
MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.
The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capaci-
tance (CRSS) and maximum output current requirement. The losses in the MOSFETs have two components:
conduction loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately
given by the following equations:
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
Where I is the load current OUT
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss.
The switching interval, tSW, is the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in
the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs. Temperature” curve of the
power MOSFET.
Layout Consideration
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept sepa-rating and finally combined using ground plane construc-
tion or single point grounding. The best tie-point between the signal ground and the power ground is at the nega-
tive side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
· Keep the switching nodes (UGATE, LGATE, BOOT,and PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals.Therefore, keep traces to these nodes as short as
possible and there should be no other weak signal traces in parallel with theses traces on any layer.

Layout Consideration (Cont.)
· The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and
discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short
and wide.
· Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce of
the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASE nodes) can
get better heat sinking.

The GND is the current sensing circuit reference ground and also the power ground of the LGATE low-

side MOSFET. On the other hand, the GND trace should be a separate trace and independently go to
the source of the low-side MOSFET. Besides, the cur-rent sense resistor should be close to OCSET pin to
avoid parasitic capacitor effect and noise coupling.
· Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example,
place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.)
· The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capaci-
tors should be close to the loads. The input capaci-tor’s ground should be close to the grounds of the
output capacitors and low-side MOSFET.
· Locate the resistor-divider close to the FB pin to mini-mize the high impedance trace. In addition, FB pin
traces can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE).

八,相关产品

Part_No	Package & Pins	Topology	Architecture	Phase	No. of PWM Outputs	Output Current (max)(A)	Input Voltage (V)		Reference Voltage(V)	Bias Voltage (typ) (V)	Quiescent Current (typ)(uA)
Part_No	Package & Pins	Topology	Architecture	Phase	No. of PWM Outputs	Output Current (max)(A)	min	max	Reference Voltage(V)	Bias Voltage (typ) (V)	Quiescent Current (typ)(uA)
JTMA7068	SOP-14	Buck	VM	1	1	30	2.9	13.2	0.9	12	8000
	QSOP-16
	QFN4x4-16
JTMA7065	SOP-8	Buck	VM	1	1	20	2.9	13.2	0.8	12	5000
JTMA7065C	SOP-8	Buck	VM	1	1	20	2.9	13.2	0.8	12	5000
JTMA7098	QFN4x4-24	Multiphase	VM	2	1	60	3.1	13.2	0.6	12	5000
JTMA7120	SOP-8	Buck	VM	1	1	20	2.2	13.2	0.8	5月12日	2100
JTMA7120A	SOP-8	Buck	VM	1	1	20	2.2	13.2	0.8	5月12日	2100
JTMA7037/A/B	SOP-8	Buck	VM	1	1	5	5	13.2	1.25 / 0.8	5月12日	3000
JTMA7037/A/B	TSSOP-8	Buck	VM	1	1	5	5	13.2	1.25 / 0.8	5月12日	3000
JTMA7057	SOP-8	Buck	VM	1	1	10	3.3	5.5	0.8	5	2100
JTMA7062B	SOP-14	Buck	VM	1	1	10	5	13.2	0.8	12	2000
JTMA7066	TSSOP-24	Buck	VM	1	2	20	5	13.2	0.6	5月12日	4000
JTMA7066	QFN5x5-32	Buck	VM	1	2	20	5	13.2	0.6	5月12日	4000
JTMA7067N	SOP-14	Buck	VM	1	1	30	2.9	13.2	0.9	12	4000
	QSOP-16
	QFN-16
JTMA7073	SOP-14	Buck	VM	1	1	30	2.2	13.2	0.6	12	5000
JTMA7073A	SOP-14	Buck	VM	1	1	30	2.2	13.2	0.6	12	5000
JTMA7074	SOP-14	Buck	VM	1	1	25	2.2	13.2	0.8	12	5000
JTMA7095/A	LQFP7x7-48	Buck	VM	1	6	0.015	1.4	6.5	-	5	1800
	TQFN7x7-48	Boost
		Flyback
JTMA7116	TSSOP-24P	Buck	VM	1	2	20	2.97	5.5	0.8	5月12日	5000
JTMA7063	SOP-14	Buck	VM	1	1	10	5	13.2	0.8	12	3000
JTMA7064	SOP-8-P	Buck	VM	1	1	30	2.9	13.2	1.2	12	3000
JTMA7064	DIP-8	Buck	VM	1	1	30	2.9	13.2	1.2	12	3000
JTMA7108	SSOP-28	Buck	VM	1	2	20	5	24	0.9	5	1200
JTMA7108	QFN4x4-24	Buck	VM	1	2	20	5	24	0.9	5	1200
JTMA7158	SOP-20	Buck	VM	1	2	20	2.2	13.2	0.6	5月12日	4000
JTMA7181	SOP-8		VM	1	2	-	-	-	-	5月12日	550
JTMA7181	DFN3x3-10		VM	1	2	-	-	-	-	5月12日	550
JTMA38HC/42/3/4/5A	DIP-8	Buck	VM	1	1	1	1.2	9	24	5	9 ~ 24
	SOP-8	Boost
		Flyback
		Forward
JTMA7138	SSOP-16	Buck	VM	1	1	25	3	25	0.6	5	1700
	QFN4x4-16
	TQFN3x3-16
JTMA7199	TDFN3x3-10	Buck	COT	1	1	25	3	25	0.5	5	350
JTMA8700	QFN4x4-24	Buck	CM	2	1	40	4.5	13.2	0.6	5月12日	4000
JTMA8720B	SOP8-P	Buck	VM	1	1	20	3	13.2	0.8	5月12日	2500
JTMA8720B	TDFN3x3-10	Buck	VM	1	1	20	3	13.2	0.8	5月12日	2500
JTMA8722A/B/C/D	SOP8-P	Buck	VM	1	1	25	3	13.2	0.6 /0.8	5月12日	1200
JTMA8723	TDFN3x3-10	Buck	VM	1	1	25	4	13.2	0.8	5月12日	2000
JTMA8724	TDFN3x3-10	Buck	COT	1	1	25	4.5	25	0.6	5月12日	80
JTMA8725/A	SOP-8P	Buck	VM	1	1	25	4.5	13.2	0.8	5月12日	16000
JTMA8726	TQFN3x3-10	Buck	VM	1	1	25	4.5	13.2	0.6	5月12日	2500
JTMA8727/L	TDFN3x3-10	Buck	COT	1	1	30	3	25	0.8	5月12日	2000
JTMA8728	TQFN3x3-16	Buck	COT	1	1	30	1.8	28	0.6	5	600
JTMA8732	QFN4x4-24	Buck	VM	2	1	50	4.5	13.2	0.6	5月12日	5000
JTMA8811	TQFN4x4-24	Buck	COT	1	2	15	6	25	2	N	550
JTMA8812	TQFN4x4-24	Buck	COT	1	2	15	6	25	2	N	550
JTMA8813/A	TQFN4x4-24	Buck	COT	1	2	20	3	28	0.75	5	800
JTMA8813/A	TQFN3x3-20	Buck	COT	1	2	20	3	28	0.75	5	800
JTMA8814	TQFN3x3-16	Buck	COT	1	1	20	1.8	28	0.75	5	400
JTMA8815	QFN3.5x3.5-14	Buck	COT	1	1	20	1.8	28	0.75	5	400
JTMA8815	TQFN3x3-16	Buck	COT	1	1	20	1.8	28	0.75	5	400
JTMA8816	TQFN3x3-16	Buck	COT	1	2	20	1.8	28	0.75	5	400
JTMA8819	QFN3x3-20	Buck	COT	1	2	20	3	28	1.8 /1.5 /0.5	5	740
JTMA8819	TQFN3x3-16	Buck	COT	1	2	20	3	28	1.8 /1.5 /0.5	5	740
JTMA8820	TQFN4x4-24	Buck	CM	1	2	15	5	28	0.5	N	3000
JTMA8820	QFN3x3-20	Buck	CM	1	2	15	5	28	0.5	N	3000
JTMA8821	TDFN3x3-10	Buck	COT	1	1	20	1.8	28	0.5	5	250
JTMA8822/C	TQFN3x3-20	Buck	COT	1	2	15	6	25	2	N	550
JTMA8823A/B	TQFN3x3-20	Buck	COT	1	2	15	5.5	25	0.6	N	50
JTMA8868	TQFN3x3-20	Buck	COT	1	2	20	3	28	0.75	5	180
JTMA7088	QFN4x4-24	Multiphase	VM	2	1	60	3.1	13.2	0.85	12	5000
JTMA7165A/B/C	SOP-8P	Buck	VM	1	1	20	2.9	13.2	0.8	12	16000
JTMA7159A	SOP-20	Buck	VM	2	2	30	10	13.2	1	12	5000
JTMA8828	TDFN3x3-10	Buck	COT	1	1	25	1.8	28	0.7	5	250
JTMA8728	TQFN 3x3 16	Buck	COT	1	1	30	1.8	28	0.6	5	600