The CXSD62117 is a dual channel voltage mode and syn-chronous PWM controller which drives dual N-channel MOSFETs. The two channels are operated with 180 de-gree phase shift.The device integrates all

发布时间:2020-04-06 09:43:38 浏览次数:702 作者:嘉泰姆 来源:1
摘要:The CXSD62117 is a dual channel voltage mode and syn-chronous PWM controller which drives dual N-channel MOSFETs. The two channels are operated with 180 de-gree phase shift.The device integrates all

目录u1q嘉泰姆

1.产品概述                       2.产品特点
3.应用范围                       4.下载产品资料PDF文档 
5.产品封装图</span>                     6.电路原理图</span>                   
7.
功能概述
                        8.相关产品

,产品概述(General Description)         
        The CXSD62117 is a dual channel voltage mode and syn-chronous
PWM controller which drives dual N-channel MOSFETs. The two channels
are operated with 180 de-gree phase shift.The device integrates all of the
control, monitoring, and protecting functions into a single package; provides
two controlled power output with over-voltage, over-temperature, and
over-current protections.
       The CXSD62117 provides excellent regulation for output load variation.
The internal 1.0V temperature-compen- sated reference voltage provides
high accuracy of 0.8% over line and temperature. The device includes a
50kHz free-running triangle-wave oscillator that is adjustable from 50kHz
to 400kHz.The CXSD62117 has been equipped with excellent pro-tection
functions: POR, OCP, UVP, and OVP protections.The Power-On-Reset (POR)
circuit can monitor the VCC and OCSET voltage to make sure the supply
voltage ex-ceeds their threshold voltage while the controller is running. The
Over-Current Protection (OCP) monitors the output current by using the
voltage drop across the high side MOSFET’s RDS(ON). When the output
current reaches the trip point, the controller will be latched. Under-Voltage
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Protection (UVP) and Over-Voltage Protection (OVP) moni-tor the FB
voltage to protect CXSD62117 from burnout when 
output voltage is
under 50% or over 120% of normal out-
put voltage. The CXSD62117
is available in SOP-20 
package.
u1q嘉泰姆

二</span>.产品特点(Features)
Single 12V Power Supply Required
Excellent Output Voltage Regulation
- 1.0V±0.8% Internal Reference Over Line and Temperature
Simple Single Loop Control Design
- Voltage Mode PWM Control 0~100% Duty Ratio
Programmable Frequency Range from 50kHz to
400kHz (Constant 50kHz when Floating)
Integrated Soft-Start and Soft-Off (Patent Pending)
Support Pre-Biased Power-On
Both Channel with 180o Phase Shift
Integrated Boot-Strap Diode
Over-Current Protection
- Sense High Side MOSFET’s RDS(ON)
120% Over-Voltage Protection
50% Under-Voltage Protection
Over-Temperature Protection
Available in SOP-20 Package
Lead Free and Green Devices Available (RoHS Compliant)

三</span>,应用范围 (Applications)
SMPS
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四.下载产品资料PDF文档 u1q嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持</span>!</span>u1q嘉泰姆

 QQ截图20160419174301.jpgu1q嘉泰姆

u1q嘉泰姆

五,产品封装图 (Package)u1q嘉泰姆


u1q嘉泰姆

六.电路原理图</span>u1q嘉泰姆

blob.pngu1q嘉泰姆

七</span>,功能概述u1q嘉泰姆

Layout Consideration
In any high switching frequency converter, a correct lay-out is important to ensure proper operation of the
regulator. With power devices switching at 200kHz, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is car-rying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnecting imped- ances and the magnitude of voltage spike. And signal and power grounds are to be kept separating till com-bined using the ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold lines
Layout Consideration (Cont.)
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indicating high current paths; these traces must be short and wide. Components along the bold lines should beu1q嘉泰姆

placed lose together. Below is a checklist for your layout:- Keep the switching nodes (UGATE, LGATE, and PHASE)away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
- The traces from the gate drivers to the MOSFETs (UGATEand LGATE) should be short and wide.
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- Place the source of the high-side MOSFET and the drainof the low-side MOSFET as close as possible. Minimiz-ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.u1q嘉泰姆

- Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closeu1q嘉泰姆

their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as
close as possible. The bulk capacitors are also placed near the drain).
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near the
loads. The input capacitor GND should be close to the lower MOSFET GND.
- The drain of the MOSFETs (VIN and PHASE nodes)should be a large plane for heat sinking.
- The ROCSET resistance should be placed near the IC as close as possible.
- The decoupling capacitor for VCC should be placed near the VCC and GND. CBOOT should be connected as
close to the BOOT and PHASE pins as possible. u1q嘉泰姆

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CXSD62106|Au1q嘉泰姆

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0.75u1q嘉泰姆

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TQFN3x3-16u1q嘉泰姆

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|QFN3x3-20u1q嘉泰姆

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CXSD62116A|B|Cu1q嘉泰姆

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1.8|1.5 1.35|1.2 0.5u1q嘉泰姆

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