CXSD6285双PWM降压控制器和一个内部线性调节器用于DDR存储器和MCH电源解决方案两个同步PWM buck控制ler驱动四个N通道mosfet

目录

1.产品概述                       2.产品特点
3.应用范围                       4.下载产品资料PDF文档 
5.产品封装图                     6.电路原理图                   
7.功能概述                        8.相关产品

一,产品概述(General Description)    

      The CXSD6285 integrates Dual PWM buck controllers and an internal linear regulator for DDR memory and MCH power solution. The two synchronous PWM buck control-lers drive four N-channel MOSFETs for DDR memory sup-ply voltage (VDDQ) and MCH regulator. The internal regu-lator is designed to track at the half of the reference volt-age with sourcing and sinking current for DDR memory termination regulator (VTT).
        The CXSD6285 uses the latched BUF_Cut signal and the POR of the BOOT to comply with ACPI power sequencing specifications. The two PWM regulators also provide POKsignals to indicate that the regulators are good. The de-vice also has the phase shift function between the two PWM controllers. The protection functions of the two PWM controllers include over-current protection, under-voltage protection, and external soft-start function. The VTT regu-lator provides 2A sinking and sourcing current-limit func-tion and also has thermal shutdown protection.
        The TSSOP-24P package with a copper pad provides excellent thermal impedance is available.
二.产品特点(Features)

1.）Provide Synchronous Rectified Buck PWM Controllers for VDDQ and        VMCH
2.）Integrated Power FETs with VTT Regulator
       Source/Sink up to 2.0A
3.）Drive Low Cost N-Channel Power MOSFETs
4.）Internal 0.8V Reference Voltage for Adjustable
      VDDQ and VMCH
5.）Thermal Shutdown
6.）VTT Tracks at Half the Reference Voltage
7.）Fixed Switching Frequency of 250kHz for VDDQ
     and VMCH
8.）Over-Current Protection and Under-Voltage
      Protection for VDDQ and VMCH
9.）Fully Complies with ACPI Power Sequencing
      Specifications
10.）180 degrees Phase Shift between VDDQ and VMCH
11.）Power-OK Function for VDDQ and VMCH
12.）Fast Transient Response
       Maximum Duty Cycle 90%
       High-Bandwidth Error Amplifier
13.）Simple Single-Loop Control Design
      Voltage Mode PWM Control
      External Compensation
14.）External Soft-Start for VDDQ and VMCH
15.）Shutdown Function for VDDQ/VTT and VMCH
16.）Thermally Enhanced TSSOP-24P Package
17.）Lead Free and Green Devices Available (RoHS Compliant)
三,应用范围 (Applications)

 DDR Memory and MCH Power Supply
四.下载产品资料PDF文档 

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五,产品封装图 (Package)

六.电路原理图

七,功能概述

Output Inductor Selection
The inductor value determines the inductor ripple current and affects the load transient response.
Higher inductor value reduces the inductor’s ripple current and induces lower output ripple voltage.
The ripple current and ripple voltage can be approximated by:where FS is the switching frequency
of the regulator.Although increases the inductor value to reduce the ripple current and voltage, there
is a tradeoff existing between the inductor’s ripple current and the regulator load tran-sient response time.
A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current.
The maximum ripple current occurs at the maximum in-put voltage. A good starting point is to choose
the ripple current to be approximately 30% of the maximum output current.Once the inductance value
has been chosen, select an inductor that is capable of carrying the required peak cur-rent without going
into saturation. In some types of inductors, especially core that is make of ferrite, the ripple current will
increase abruptly when it saturates. This will result in a larger output ripple voltage.
Output Capacitor Selection
Higher Capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore,
select high performance low ESR capacitors are intended for switch-ing regulator applications.
In some applications, mul-tiple capacitors have to be parallelled to achieve the de-sired ESR value.
A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the
voltage rating of the output capacitors also must be considered. If tantalum capacitors are used,
make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer.
Input Capacitor Selection
The input capacitor is chosen based on the voltage rat-ing and the RMS current rating. For reliable
operation,select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is approximately IOUT/2,where IOUT is the load current.
During power-up, the input capacitors have to handle large amount of surge current.
If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt,
consult the ca- pacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1μF can be
connected between the drain of upper MOSFET and the source of lower MOSFET.
MOSFET Selection
The selection of the N-channel power MOSFETs are de-termined by the RDS(ON), reverse transfer
capacitance(CRSS)and maximum output current requirement. The losses in the MOSFETs have two
components: conduction loss and transition loss. For the upper and lower MOSFET, the losses are
approximately given by the following equations:
MOSFET Selection (Cont.)
PUPPER = IOUT 2(1+ TC)(RDS(ON))D + (0.5)(IOUT)(VIN)(tSW)FS
PLOWER = IOUT 2(1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while the upper MOSFET includes an additional transition
loss.The switching internal, tSW, is the function of the reverse transfer capacitance CRSS. The (1+TC) term
is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs
Temperature” curve of the power MOSFET.
Layout Consideration
In high power switching regulator, a correct layout is im-portant to ensure proper operation of the regulator. In
general, interconnecting impedances should be mini-mized by using short and wide printed circuit traces. Sig-
nal and power grounds are to be kept separating and finally combined to use ground plane construction or
single point grounding. Figure 14 illustrates the layout,with bold lines indicating high current paths; these traces
must be short and wide. Components along the boldlines should be placed close together.
Below is a checklist for your layout:
·-The metal plate of the bottom of the packages (TSSOP-24P) must be soldered to the PCB and con-nect to
the GND plane on the backside through sev-eral thermal vias. More vias is better for heatsink.
·-Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore,keep traces to these nodes as short as possible.
· Connet the FB and VTTFB to point of load and the REFSEN should be connected to the point of load of
the VDDQ output.
· The traces from the gate drivers to the MOSFETs (UG1,LG1, UG2, and LG2) should be short and wide.
Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and SS capacitors
should be close to their pins.
The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near
the loads.
The input capacitor GND should be close to the out-put capacitor GND and the lower MOSFET GND.
The drain of the MOSFETs (VIN and phase nodes)
should be a large plane for heat sinking.

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