CXSD6290全桥配置中驱动两个高侧P通道和两个低侧N通道mosfet输出由PWM1和PWM2输入独立控制

目录

1.产品概述                       2.产品特点
3.应用范围                       4.下载产品资料PDF文档 
5.产品封装图                     6.电路原理图                   
7.功能概述                        8.相关产品

一,产品概述(General Description)   

       The CXSD6290 is designed to drive two high-side P-chan-nel
MOSFETs and two low-side N-channel MOSFETs in a full-bridge
configuration. The outputs are independently controlled by PWM1
and PWM2 input signals.The other features include VCC power-
on-reset and ther-mal shutdown.
二.产品特点(Features)

1.)Wide Input Voltage Range: 4.5V to 13.2V
2.)Drives a Full-Bridge Inverter(High-Side P-
3.)Channel MOSFETs and Low-Side N-Channel MOSFETs)
4.)Thermal Shutdown Protection
5.)VCC Power-On-Reset SOP-8 Package
6.)Lead Free and Green Devices Available
三,应用范围 (Applications)

 LCD Monitor and LCD TV
四.下载产品资料PDF文档 

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五,产品封装图 (Package)

FUNCTION

六.电路原理图

七,功能概述

Thermal Shutdown
shutdown circuit will pull PGATE outputs high and NGATE outputs low thus turning high-side and low-side
MOSFET off. When the driver cools down below 110ïC after a ther-mal shutdown, it resumes normal operation
and follows the PWM input signals.
Power-On-Reset (POR)
The CXSD6290 provides the power-on-reset function that keeps the driver disable when the VCC voltage
is insuffi-cient to driver external MOSFETs reliably. The PGATE out-puts remain high and the NGATE outputs
remain low until the VCC voltage exceeds POR threshold. Once the POR threshold is reached, the condition
of gate driver outputs is defined by the PWM signals.
Layout Consideration
In any high switching frequency application, a correct lay-out is important to ensure proper operation of the
device.With power devices switching at high frequency, the re-sulting current transient will cause voltage
spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the
turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is car-rying the full load current. During
turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode.
Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general,
using short and wide printed circuit traces should minimize interconnecting imped-ances and the magnitude of
voltage spike. Below is a checklist for your layout :
- Keep the switching nodes (PGATE, NGATE and the drain of the MOSFETs) away from sensitive small sig-
nal nodes (PWM1, PWM2, MS, and DTC ) since these nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
- Place the drain of the P-MOSFET and the drain of the N-MOSFET as close as possible to minimize the imped
ance with wide layout plane between the two pads and reduce the voltage bounce of the node.
- The traces from the gate drivers to the MOSFETs (PGATE and NGATE) should be short and wide.
- The VCC decoupling capacitor (C7), C5, C6, and RDTC should be close to their pins.
- The input capacitor should be near the source of the P-MOSFET.
- The drain of the MOSFETs should be a large plane for heat sinking.
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